EE/CS 120A: Logic Design | Summer 2006 |
Webpages for previous course offerings (Winter 2005, Summer 2005, Winter 2006)
Subject area: EE/CS | Course number: 120A | Section number: 101 | |
Course title: LOGIC DESIGN | Units: 5 | ||
Call number: 10561/10363 | Instructor(s): Fonoberov V | ||
Class type: LEC | Day: MTWR | Time: 8:00 - 9:30 a.m. | Location: SPR 2355 |
Final exam: 07/28/2006 8-10 a.m. | Max enrollment: 56 Seats Available: 41 |
Status: Open | |
Activity Control: REGISTRATION REQUIRED FOR LEC, LAB | |||
Prerequisite(s): CS 061 with a grade of "C-" or better | |||
UCR General Catalog 2005-2006:
EE/CS 120A. Logic Design 5 Lecture, 6 hours; laboratory, 12 hours. Prerequisite(s): CS 061 with a grade of "C-" or better. Covers the design of digital systems. Topics include Boolean algebra; combinational and sequential logic design; design and use of arithmetic-logic units, carry-lookahead adders, multiplexors, decoders, comparators, multipliers, flip-flops, registers, and simple memories; state-machine design; and basic register-transfer level design. Laboratories involve use of hardware description languages, synthesis tools, programmable logic, and significant hardware prototyping. |
Lecture:
Section 101: MTWR 8:00 - 9:30 p.m., SPR 2355
Instructor: Dr. Vladimir Fonoberov
(vladimir.fonoberov@ucr.edu)
Office hours: Tuesday 1:00 - 3:00 p.m., ENGR2 222
Labs:
Section 121: MTWR 10:00 a.m. - 1:00 p.m., ENGR2 125
Teaching Assistant: Xiaoli Zhou (xzhou@ee.ucr.edu)
Office hours: to be announced
Section 122: MTWR 3:00 - 6:00 p.m., ENGR2 125
Teaching Assistant: Yuying Gao (ygao001@student.ucr.edu)
Office hours: to be announced
Text:
"Digital Design (Preview Edition)" by Frank Vahid, John Wiley & Sons,
Inc., 2006 (ISBN 0-471-46784-7)
Course grading:
The course consists of 100 points:
Grades will be assigned as follows: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F (+/- grades will be given).
(subject to change as the quarter progresses)
(subject to change as the quarter progresses)
Read the lab overview and report format.
Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C
Last modified: June 26, 2006; 10:32 PM