EE/CS 120A: Logic Design | Summer 2005 |
Webpage for previous course offering (Winter 2005)
Subject area: EE/CS | Course number: 120A | Section number: 101 | |
Course title: LOGIC DESIGN | Units: 5 | ||
Call number: 10563/10389 | Instructor(s): Fonoberov V | ||
Class type: LEC | Day: MTWTh | Time: 8:00-9:30am | Location: Sproul Hall 2355 |
Final exam: Fri. 7/22/2005 8:00-10:00am | Max enrollment: 50 Seats Available: 18 |
Status: Open | |
Activity Control: REGISTRATION REQUIRED FOR LEC, LAB | |||
Prerequisite(s): CS 061 with a grade of "C-" or better | |||
UCR General Catalog 2004-2005:
EE/CS 120A. Logic Design 5 Lecture, 6 hours; laboratory, 12 hours. Prerequisite(s): CS 061 with a grade of "C-" or better. Covers the design of digital systems. Topics include Boolean algebra; combinational and sequential logic design; design and use of arithmetic-logic units, carry-lookahead adders, multiplexors, decoders, comparators, multipliers, flip-flops, registers, and simple memories; state-machine design; and basic register-transfer level design. Laboratories involve use of hardware description languages, synthesis tools, programmable logic, and significant hardware prototyping. |
Lecture:
Section 101: MTWTh 8:00 - 9:30 a.m., Sproul Hall 2355
Instructor: Dr. Vladimir Fonoberov
(vladimir.fonoberov@ucr.edu)
Office hours: Wed 2:00 - 3:00 p.m., Bourns Hall B235B
Labs:
Section 121: MTWTh 10:00 a.m. - 1:00 p.m., Bourns Hall B156
Teaching Assistant: Rong Wang (rwang@ee.ucr.edu)
Office hours: to be announced, Bourns Hall B156
Section 122: MTWTh 3:00 - 6:00 p.m., Bourns Hall B156
Teaching Assistant: Zhuo Zhao (zhaozhuo@ee.ucr.edu)
Office hours: to be announced, Bourns Hall B156
Text:
"Digital Design" by Frank Vahid (ISBN
0-471-70831-3)
Course grading:
The course consists of 100 points:
Grades will be assigned as follows: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F (+/- grades will be given).
(subject to change as the quarter progresses)
Datapath Components
(subject to change as the quarter progresses)
Read the lab overview and report format.
Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C
Last modified: June 20, 2005; 05:02 PM